orderin g numbe r : ena1515 bi-cmos ic for vcms constant-current driver ic LV8098CS overview the LV8098CS is a constant current driver ic for voice coil motors that supports i 2 c control integrating a digital/analog converter (dac). it uses an ultraminia ture wlp package and includ es a current detection resi stor for constant current control, which makes the ic ideal for miniaturization of camera modules intended for use in camera-equipped mobile phones. the output transistor has a low on-resistance of 1 and the resistance of the built-in current detection resistor is 1 , which minimizes the voltage loss and helps withstand voltage drop in v cc . the current consumption when the dac is set to code 0 is 0 (i cc 0, i out 0) allowing reduction in current consumption. functions ? constant current driver for voice coil motors. ? constant current control enabled by dac (8 bits). ? i 2 c bus control supported. ? wide operating voltage range (2.2 to 5.0v). ? the current consumption is 0 when the dac is set to code 0. ? 6-pin wlp package used (1.27 0.87 0.5mm). ? built-in thermal protection circuit. ? built-in voltage drop protection circuit (v cc = 2v output off). ? low output block total-resistance of 2 helps withstand voltage drop in v cc . (current detection resistance + output transistor on-resistance). ? built-in current detection resistor. specifications absolute maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v cc max 5.5 v output voltage v out max v cc + 0.5 v input voltage v in max scl, sda, ena 5.5 v allowable power dissipation pd max with specified substrate * 350 mw operating temperature topr -30 to +85 c storage temperature tstg -40 to +150 c * specified substrate : 40mm 40mm 1.6mm, single layer glass epoxy substrate specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use. 72909 sy pc 20090626-s00003 no.a1515-1/8
LV8098CS allowable operating conditions at ta = 25 c parameter symbol conditions ratings unit supply voltage v cc 2.2 to 5.0 v maximum preset output current i o 100 ma high-level input voltage v ih 1.3 to v cc v low-level input voltage v il applied to scl, sda, and ena pins -0.3 to 0.5 v electrical characteristics at ta = 25c, v cc = 2.8v ratings parameter symbol conditions min typ max unit i cco a ena = l 1 a i cco b ena = h, pd = 1 1 a i cco c ena = h, d0 to d7 = 0 1 a supply current i cc 1 ena = h, d0 to d7 0 0.5 3 ma input current i in scl, sda, ena -1 0 1 a total resistance value of the output block (built-in resistor + transistor on-resistance) rttl v cc = 2.8v, i out = 80ma 2 3 dac block resolution 8 bits relative accuracy inl 1 lsb differential linearity dnl 1 lsb full code current ifull d0 to d7 = 1 100 ma error code current 0 izero d0 to d7 = 0 1 a spark killer diode reverse current is (leak) 1 a forward voltage vsf 1.3 v package dimensions unit : mm (typ) 3380 pd max -- ta 0 0.3 0.35 0.18 0.2 0.1 0.4 --30 --20 80 100 60 20 40 0 120 ambient temperature, ta -- c allowable power dissipation, pd max -- w specified board : 40 40 1.6mm 3 single layer glass epoxy sanyo : wlp6(1.27x0.87) 0.4 ab 0.4 0.24 0.24 0.2 0.87 1.27 0.5 max 0.12 top view side view side view bottom view laser marked index 12 3 no.a1515-2/8
LV8098CS pin assignment pin no. pin name pin description a1 scl i 2 c scl input pin a2 ena enable & reset *1, 2 a3 gnd ground b1 sda i 2 c sda input pin b2 v cc power supply pin b3 out output pin 0.4 3 # p u u p n view ( ball side up ) 2 1 1.27 0.87 0.4 a b *1 : setting the ena pin to low powers down and resets the ic. it is necessary to power on the ic by setting the ena pin to low and hold it high during normal operation. *2 : when the ena pin is to be used with pull_up, it is necessary to send code 0 in advance after power-on. block diagram i 2 c if c p u i 2 c decode gnd v cc 0.1f sda ena scl rf out vcm 1 dac 8 bits current setting reference voltage voltage drop protection & thermal protection - + bias no.a1515-3/8
LV8098CS pin description pin no. pin name description equivalent circuit a1 a2 scl ena scl i 2 c serial clock input pin enable when low, standby mode and reset is performed at the same time. this pin is held high for normal use. input high level : 1.3v to 5.0v input low level : -0.3v to 0.5v a3 gnd ground pin. b3 out out output pin this is an nmos open drain output, and the voice coil motor is connected between this pin and the v cc pin for use. v cc 1 b3 b2 v cc v cc power supply input pin b1 sda sda i 2 c serial data input pin input high level : 1.3v to 5.0v input low level : -0.3v to 0.5v v dd gnd a1 a2 v dd gnd b1 no.a1515-4/8
LV8098CS serial bus communication specifications i 2 c serial transfer timing conditions standard mode th1 ton ts2 th2 twh twl sda scl start condition input waveform condition stop condition ts1 ts3 th1 resend start condition tbuf tof standard mode parameter symbol conditions min typ max unit scl clock frequency fscl scl clock frequency 0 100 khz ts1 setup time of scl with respect to the falling edge of sda 4.7 s ts2 setup time of sda with respect to the rising edge of scl 250 ns data setup time ts3 setup time of scl with respect to the rising edge of sda 4.0 s th1 hold time of scl with respect to the rising edge of sda 4.0 s data hold time th2 hold time of sda with respect to the falling edge of scl 0 s twl scl low period pulse width 4.7 s pulse width twh scl high period pulse width 4.0 s ton scl, sda (input) rising time 1000 ns input waveform conditions tof scl, sda (input) falling time 300 ns bus free time tbuf interval between stop condition and start condition 4.7 s high-speed mode parameter symbol conditions min typ max unit scl clock frequency fscl scl clock frequency 0 400 khz ts1 setup time of scl with respect to the falling edge of sda 0.6 s ts2 setup time of sda with respect to the rising edge of scl 100 ns data setup time ts3 setup time of scl with respect to the rising edge of sda 0.6 s th1 hold time of scl with respect to the rising edge of sda 0.6 s data hold time th2 hold time of sda with respect to the falling edge of scl 0 s twl scl low period pulse width 1.3 s pulse width twh scl high period pulse width 0.6 s ton scl, sda (input) rising time 300 ns input waveform conditions tof scl, sda (input) falling time 300 ns bus free time tbuf interval between stop condition and start condition 1.3 s no.a1515-5/8
LV8098CS i 2 c bus transmission method start and stop conditions the i 2 c bus requires that the state of sda be preserved while scl is high as shown in the timing diagram below during a data transfer operation. ts2 th2 scl sda when data is not being transferred, both scl and sda are in the high state. the start condition is generated and access is started when sda is changed from high to low while scl and sda are high. conversely, the stop condition is generated and access is e nded when sda is changed from low to high while scl is high. th1 th3 scl sda start condition stop condition data transfer and acknowledgement response after the start condition has been generated, the data is tr ansferred one byte (8 bits) at a time. generally, in an i 2 c bus, a unique 7-bit slave address is assigned to each device, and the firs t byte of the transfer data is allocated to the 7-bit slave address and to the command (r/w) indicating the transfer direction of the subsequent data. however, this ic is provided with only a write mode for receiving the da ta. every time 8 bits of da ta for each byte are transf erred, the ack signal is sent from the receiving end to the sending end. immediately after the clock pulse of scl bit 8 in the data transferred has fallen to low, sda at the sending end is re leased, and sda is set to low at the recei ving end, causing the ack signal to be sent. when, after the receiving end has sent the ack signal, the transfer of the next byte re mains in the receiving status, the receiving end releases sda at the falling edge of the ninth scl clock. m s b l s b a c k l s b a c k m s b m s b l s b a c k w data x : don't care a1 scl sda (write) data slave address 2nd byte 3ed byte 1st byte start stop a2 a3 a4 a5 a6 a7 0 pd x d7d6d5d4d3d2 d1 d0xxxxxx no.a1515-6/8
LV8098CS no.a1515-7/8 the standard data transfer to this device consists of three by tes : the slave address of the first byte and the data of the second and third bytes. slave address : 0110011(0) pd : power-down d1-d7 : 8-bit data used to set output constant current ; min = 00000000, max = 11111111 the table below shows the format of the second and third bytes. 2nd byte 3rd byte serial data bits sd7 sd6 sd5 sd4 sd3 s d2 sd1 sd0 sd7 sd6 sd5 sd4 sd3 sd2 sd1 sd0 function pd d7 d6 d5 d4 d3 d2 d1 d0 pd bit setting method pd = 1 power_down (standby mode) and reset d0-d7 setting method current setting code d7 d6 d5 d4 d3 d2 d1 output setting (lsb) output current (ma) (design value) 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0.392 2 0 0 0 0 0 1 0 2 0.784 254 1 1 1 1 1 1 0 254 99.608 255 1 1 1 1 1 1 1 255 100 relationship between the ena pin input, i 2 c input data pd, and current setting 0 (code 0) this ic supports the following three modes of setting up the standby mode : 1) setting the ena pin low. 2) setting the pd bit to 1 (high) with i 2 c input data. 3) setting the output current to 0 with i 2 c input data. execution of one of the steps 1) to 3) causes the output current to 0 and stops operation of the circuit. when the ena pin is set low, the i 2 c data register is reset and the ic is reset to its default state (pd bit set to 0 and output current setting to code 0). since the ic starts operation in the data reset state at power- on time, it is necessary to start using the ic in the default st ate by setting the ena pin low before turning on v cc and then high after v cc is established.
LV8098CS sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rate d values (such as maximum ra tings, operating condition ranges, or other parameters) listed in products specif ications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qual ity high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. it is possible that these probabilistic failures or malfunction could give rise to acci dents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention c ircuits for safe design, redundant design, and structural design. upon using the technical information or products descri bed herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable f or any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagr ams and circuit parameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equi pment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor c o.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities conc erned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any in formation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd. this catalog provides information as of july, 2009. specifications and informat ion herein are subject to change without notice. ps no.a1515-8/8
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